RV32I Pipelined Core

A from-scratch implementation of the RV32I base integer ISA as a classic in-order pipeline (IF / ID / EX / MEM / WB), built to understand the digital design flow end-to-end — and one I'm now working toward taping out.

Problem

I wanted to understand a CPU at the level where you can't hand-wave anything: write the RTL, handle the hazards yourself, and prove it runs real instructions in simulation rather than trusting that it "should" work.

Approach

• Microarchitecture. Multi-stage in-order pipeline with forwarding and a load-use hazard interlock, with control logic to flush on taken branches.
• Datapath. Register file, ALU, immediate generation, and a memory interface built up from the ISA spec to cover the RV32I instruction set.
• Verification. Self-checking testbenches that run instruction sequences and compare architectural state against expected results, inspecting waveforms to trace hazards and control bugs.

Result

• Executes RV32I instruction sequences correctly in simulation with hazards resolved.
• Forms the basis of an ongoing effort to push the design through a synthesis and physical-design flow toward a tape-out.

What's next: harden the core through an open-source ASIC flow, close timing on a target PDK, and produce a tape-out-ready layout.