2025/Solo — ML, RTL, and deployment
FPGA-Accelerated Digit Recognizer
A handwritten-digit neural network trained from scratch in NumPy, then quantized and deployed to a Zynq-7000 FPGA for parallel hardware inference.
VerilogVivadoZynq-7000PythonNumPyQuantization
Verilog
A handwritten-digit recognizer taken the whole way down the stack: a neural network built from first principles in software, then re-implemented as a quantized inference engine running on an FPGA.
Problem
Most ML projects stop at a trained model on a GPU. I wanted to understand what it actually takes to run inference in hardware — the quantization, the dataflow, and the control logic — by building both the model and the accelerator myself.
Approach
- Model from scratch. A 3-layer fully-connected network in Python / NumPy with hand-coded backpropagation and gradient descent, using ReLU and Softmax with cross-entropy loss for stable multi-class training.
- Quantization. Converted the trained network to an int8 / int32 fixed-point representation suitable for integer-only hardware.
- Hardware. Verilog implementation on a Zynq-7000 SoC FPGA in Vivado, with a custom FSM-controlled UART IP to stream image data in and parallel MAC datapaths to perform inference, surfacing the result on real-time LED output.
Result
- 92% accuracy on the MNIST dataset from the from-scratch software model.
- Quantized network deployed on the Zynq-7000, streaming images over UART and classifying digits in hardware.
What's next: widen the parallel datapath and pipeline the MAC stages to push throughput higher.